EC2354 VLSI Design Important Questions
Unit-I
CMOS Technologies and Process Enhancement
Layout Design Rules
Technology related CAD issues
Manufacturing issues
Unit – II
Device Characteristics
Circuit Characteristics
Interconnect Simulation
Spice Tutorial
Device Model
Unit – III
Low power logic Design
Sequence static circuit
Circuit design of latches and flip-flop
Unit – IV
Logic verification
Design for testability
Boundary Scan
Unit – V
D Latch and D flip flop
Structural Gate level switch level modeling
RTL Modeling
Half adder & Full adder
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